The present invention relates generally to integrated circuits. More particularly, the present invention provides a circuit and method for a CMOS interpolator for an output clock signal with a desirable phase for a high speed serializer/deserializer device. But it will be recognized that the technique can be used for regulating memory devices (e.g., DDR 4 SDRAM devices, DDR4 register devices, DDR4 controller devices), and other high speed data applications.
Over the last few decades, the use of communication networks exploded. In the early days of the Internet, popular applications were limited to emails, bulletin board, and mostly informational and text-based web page surfing, and the amount of data transferred was usually relatively small. Today, Internet and mobile applications demand a huge amount of bandwidth for transferring photo, video, music, and other multimedia files. For example, a social network like Facebook processes more than 500 TB of data daily.
With high demand for communication networks came high demand for quality networking devices. One of the critical components of network devices is phase interpolator. For example, a phase interpolator is often used as a critical circuit in the receiver of the serial link that allows the receiver to adjust the phase of its sampling clocks in fine increments. Over the past, various types of phase interpolators have been proposed and implemented. For example, conventional phase interpolators include voltage controlled interpolators and current controlled interpolators. Among other things, conventional phase interpolators are usually complex and require large amount of power to operate.
Therefore, it is desirable to have new and improved phase interpolators.